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EG6599S

Chip Features 50% duty cycle, frequency control resonant half-bridge High-precision oscillator, operating frequency up to 500kHz Two-stage OCP, frequency shift and latch off Interface with PFC controller Latch disable input Burst mode protection at light load With soft start protection and power-down protection With high-voltage line voltage protection High-side 650V gate driver -0.3A/0.8A high-side and low-side gate drive Lead-free and halogen-free, RoHS compliant Package: SOP16L


  • Product Description
    • Commodity name: EG6599S
    • 封装: SOP16L
    • 品牌: EG/Yi Jing Wei

    Chip Features 50% duty cycle, frequency control resonant half-bridge High-precision oscillator, operating frequency up to 500kHz Two-stage OCP, frequency shift and latch off Interface with PFC controller Latch disable input Burst mode protection at light load With soft start protection and power-down protection With high-voltage line voltage protection High-side 650V gate driver -0.3A/0.8A high-side and low-side gate drive Lead-free and halogen-free, RoHS compliant Package: SOP16L

    Chip Description

    The EG6599S is a dual-ended controller specifically designed for resonant half-bridge topology. It provides a 50% complementary duty cycle, with equal on-times for the high-side and low-side switches, a 180° phase difference between them, and output voltage adjustment through modulation of the operating frequency. A fixed dead time ensures soft switching and high-frequency operation; an external oscillator sets the converter's operating frequency, and a built-in bootstrap diode is included. During startup, to prevent uncontrolled surge current, the switching frequency starts at its maximum and gradually decays, reaching a steady-state value determined by the control loop. This frequency shift is non-linear, minimizing output voltage overshoot, and the duration is programmable. The IC can be forced into controlled burst-mode operation under light loads to keep the converter's input power consumption to a minimum. IC features include a non-latching active-low disable input, current limiting and undervoltage protection, current sensing input, frequency auto-restart, switching, and delayed shutdown. A higher-level OCP will latch the IC primary current if the first level of protection is insufficient to control the IC. Their combination provides a complete overload and short-circuit protection circuit. An additional latching disable input (DIS) facilitates easy implementation of OTP or OVP. An interface with a PFC controller is provided, allowing shutdown in fault conditions such as OCP shutdown and DIS high, or operation during burst mode.

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